The present invention relates generally to semiconductor memory devices, and, more particularly, to a semiconductor memory device having an improved flash write mode.
Various types of semiconductor memory devices, e.g., video RAMs, employ a flash write mode for concurrent processing of large amounts of data. The flash write mode resets data stored in a large number of memory cells to a "high" logic level (hereinafter referred to simply as either "high" or "high level") or a "low" logic level (hereinafter referred to simply as either "low" or "low level"). In the flash write mode, it is possible to reset all of the memory cells which are connected to a selected word line, during a single/RAS cycle.
With reference now to FIG. 1, there can be seen a schematic block diagram of a semiconductor memory device which includes a conventional flash write circuit. As can be seen in FIG. 1, the memory device is divided into four memory blocks 100. Column address signals for designating bit lines of the memory device are applied to a column address buffer 101, and the buffered column address signals output by the column address buffer 101 are applied to a column decoder 102. The column decoder 102 decodes the buffered column address signals to generate column designation signals DCAi (where, i=0-n) and then ORs the column designation signals with a flash write control signal FLW to generate column selection (or, column select) signals DCAi' (where, i'=0-n). The number of column designation and column selection signals is equal to the number of bit lines. The respective column selection signals DCAi' are transmitted to corresponding column selection signal lines CSLi (where, i=0-n), and are applied to the control gate of respective column selection gates 104 connected between a common data input/output line and respective ones of the bit lines in the memory blocks 100. The column selection signals CSLi are shared in common by the memory blocks 100 and thus, the column decoder 102 controls the column selection gates of all of the memory blocks 100.
With reference now to FIG. 2, there can be seen a detailed circuit diagram of the column decoder 102 for Oring the decoded column designation signals DCAi with the flash write control signal FLW. The column designation signals DCAi are respectively applied to first input terminals of n+1 NOR gates 201 and tile flash write control signal FLW is commonly applied to second input terminals of the respective NOR gates 201. The respective output signals of the NOR gates 201 are inputted to corresponding n+1 inverters 203. The output of the inverters 203 are the column selection signals DCAi'. Therefore, if the flash write control signal FLW is high, all of the column selection signals DCAi' are also high.
With reference now to both FIGS. 1 and 2, when the flash write control signal FLW is low, i.e., when the flash write mode is not enabled, the logic level of the column selection signals DCAi' are determined by the logic level of the corresponding column designation signals. In operation, a single column selection signal corresponding to the decoded column address signals which identify the selected column, is driven high. To the contrary, when the flash write control signal FLW is high, i.e., when the flash write mode is enabled, all of the column selection signals DCAi are driven high, so that all of the column selection lines CSLi are driven high, and thus, all of the corresponding column selection gates 104 are turned on. As a result, if data of a high logic level or a low logic level is applied to the common data input/output line, that data is written into all of the memory cells of a selected word line of a selected memory block 100.
As will be appreciated by those skilled in the art, since all of the column selection lines are simulaneously turned, the conventional flash write circuit generates high peak current and suffers from noise problems associated therewith. Thus, current consumption is unduly high and the reliability of the memory device is impaired.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a flash write circuit for a semiconductor memory device which overcomes the above-mentioned shortcomings and drawbacks of the conventional flash write circuit. The present invention fulfills this need.